BATMAN: Maximizing Bandwidth Utilization of Hybrid Memory Systems. CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache. PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access. Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms. Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization. Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM. Configuring Huge Pages in Red Hat Enterprise Linux 4 or 5. PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture. A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing. Unlocking Bandwidth for GPUs in CC-NUMA Systems. Page Placement Strategies for CPUs within Heterogeneous Memory Systems. IntelВ® 64 and IA-32 Architectures Optimization Reference Manual.NVLink, Pascal and Stacked Memory: Feeding the Appetite for Big Data.Our evaluations show that Banshee significantly improves performance (15% on average) and reduces DRAM traffic (35.8% on average) over the best-previous latency-optimized DRAM cache design. Second, it reduces unnecessary DRAM cache replacement traffic with a new bandwidth-aware frequency-based replacement policy. First, it eliminates the tag lookup overhead by tracking the contents of the DRAM cache using TLBs and page table entries, which is efficiently enabled by a new lightweight TLB coherence protocol we introduce. We propose a new DRAM cache design, Banshee, that optimizes for both in-package and off-package DRAM bandwidth efficiency without degrading access latency. Hence, as we show in this paper, these designs are suboptimal for use with in-package DRAM. Unfortunately, most previous DRAM cache designs optimize mainly for cache hit latency and do not consider bandwidth efficiency as a first-class design constraint. A promising use of in-package DRAM is as a large cache. Yet, the latency of in-package DRAM is not appreciably lower than that of off-package DRAM.

Placing the DRAM in the same package as a processor enables several times higher memory bandwidth than conventional off-package DRAM.

Banshees fast and low